1. Field of the Invention
The present invention relates to a semiconductor storage device, and particularly relates to a semiconductor storage device suitably applied to a 1.5 port SRAM (Static Random Access Memory).
2. Description of Related Art
In a conventional semiconductor storage device, as disclosed in Japanese Unexamined Patent Application Publication No. 10-247691 for example, there has been a method for constituting an SRAM as below. In the method, four (4) n-channel type transistors and two (2) p-channel type transistors are used. Of these transistors, two (2) n-channel type transistors are used as a driver transistor, the remaining two (2) n-channel type transistors are used as a transfer gate, and the two (2) p-channel type transistors are used as a load transistor, such that an SRAM is constituted.
The driver transistor and load transistor constitute a CMOS inverter where a p-channel type transistor and an n-channel type transistor are coupled to each other in series. A pair of CMOS transistors cross-coupled to each other constitutes a flip-flop.
Meanwhile, there has been a method for constituting a 1.5 port SRAM capable of reading out without depending on a signal of a word line. In the method, one (1) p-channel type transistor is further added to the four (4) n-channel type transistors and two (2) p-channel type transistors, and the added p-channel type transistor is used as a reading-out transistor.
In the 1.5 port SRAM, in order to reduce the area of a memory cell, a gate electrode of one CMOS inverter, which comprises the driver transistor and load transistor, is bent in an L-shape so as to be used as a gate electrode of the reading-out transistor.
However, in the case where a gate electrode of one CMOS inverter comprising the driver transistor and load transistor is used as a gate electrode of a reading-out transistor, the shape of a gate electrode of one CMOS inverter comprising the driver transistor and load transistor is different from the shape of a gate electrode of the other CMOS inverter comprising the driver transistor and load transistor.
Thus, in some cases, a difference in transistor characteristic may be caused between the pair of n-channel type transistors used as a driver transistor, or between the pair of p-channel type transistors used as a load transistor because of a variation in the patterning of the gate electrodes. As a result, the reading and writing operation of the 1.5 port SRAM may be disturbed.
The present invention therefore is intended to provide a semiconductor storage device that can reduce the difference in characteristics caused between transistors even in the case where the shapes of gate electrodes are different from each other.